Intel shares process roadmap leading to the Angstrom Era


An Intel Speeded up webcast went continue to exist Monday, with plenty of vital bulletins. The hour-long live-streamed tournament defined Intel’s plans to switch-up its node naming technique to be extra significant, and make it seem to be extra in line with the likes of TSMC and Samsung. Moreover, Intel shared details about two step forward applied sciences dubbed RibbonFET and PowerVia, and it mentioned its expanded/optimised Foveros three-D stacking applied sciences. Finally, it welcomed large hitters Qualcomm and Amazon AWS as Intel Foundry Products and services (IFS) consumers.

Above, you’ll be able to see the new node naming scheme from Intel. The following technology client desktop and pc CPUs from Intel, the Alder Lake processor circle of relatives, would possibly not be referred to as Intel Enhanced 10nm SuperFin chips after they release later this 12 months – as an alternative they’re going to be the first ‘Intel 7’ processors (as will Sapphire Rapids information centre CPUs).

Explaining the trade, Intel says that the new scheme will “give consumers a extra correct view of process nodes throughout the trade,” and that is all the extra vital now that IFS has been established. It subsidized up its claims of the new naming scheme being higher / extra suitable with quotes from journals like Semiconductor Engineering and IEEE Spectrum. TSMC’s VP of company analysis, Philip Wong used to be quoted too, pronouncing “These days those numbers are simply numbers. They are like fashions in a automobile… it is only a designation for the subsequent generation node… So let’s now not confuse the title of the node with what the generation if truth be told gives”. TSMC prefers to use its ‘Nx’ naming scheme, relatively than use nanometers.

Transferring alongside Intel’s roadmap, you’ll be able to see that to the a ways proper, the ‘Angstrom Era’ begins with Intel 20A in approx H1 2024. This additionally ushers in some vital applied sciences. RibbonFET, Intel’s implementation of a gate-all-around transistor, will likely be the corporate’s first new transistor structure because it pioneered FinFET in 2011. Intel says this design “delivers quicker transistor switching speeds whilst reaching the identical force present as more than one fins in a smaller footprint”. PowerVia will debut at Intel 20A too. Intel says that PowerVia makes use of chip via by way of channels to ship energy from the rear of the chip, getting rid of energy routing from the entrance facet of the wafer.

A 12 months or so after Intel 20A, we will have to be expecting Intel 18A, which is already in construction for early 2025. It is going to debut refinements to RibbonFET for a “primary bounce in transistor efficiency”. Intel is operating carefully with ASML on different ‘past EUV’ tech, too.

On the subject of complementary tech, Intel is constant to refine and optimise its three-D chip packaging. It is going to advance Foveros three-D stacking tech with; Foveros Omni for blending more than one most sensible die tiles with more than one base tiles throughout blended fab nodes, and Foveros Direct which “strikes to direct copper-to-copper bonding for low-resistance interconnects and blurs the boundary between the place the wafer ends and the place the package deal starts,” in accordance to the chipmaker.

Intel additionally took the time to supply updates on its industry development since IDM 2.0 and IFS used to be introduced. It sounds as if to have already coated up two large consumers for its products and services; Qualcomm for SoC manufacturing the usage of Intel 20A, and Amazon AWS for IFS packaging answers.

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